Shrinking of transistor size can enable smaller, faster, more power-efficient and cost-efficient microelectronic devices. However, as transistor size gets smaller and approaches practical limits, changes to device architecture, such as the design of transistor gates can be used to further improve device performance and provide greater integration density. For example, as transistor size gets smaller, the gate head width (Wgh) will get smaller and the current capacity (Id) and the transconductance (gm) will be reduced while the parasitic capacitance will generally also be reduced and the potential speed of the device increases. Accordingly, to regain current capacity and transconductance lost due to shrinking the size of the device, ways of achieving the effect of a wider gate head are desired without actually increasing the width of the gate head and increasing the size of the transistor.
One approach to improve device performance, such as increasing the current capacity and/or transconductance, can include expanding transistor gate-width such as by multiplying the number of gates, by utilizing multiple gate-fingers, which can boost current and reduce gate resistance. However, such designs can lead to increased parasitic capacitance and can adversely impact high-frequency characteristics of the device. Further, in some cases such approaches can result in a complicated layout and a larger footprint for the resulting device.
Additional approaches for increasing transistor performance are desired.